As data rates in computing devices increase and power budgets decrease, various design objectives are in opposition. For example, in the design and implementation of high-speed interconnects that are used to communicate data within and to and from integrated circuits and other components of one or more systems, voltage and timing eye margins become tighter. Consequently, resulting interconnects are more sensitive and may suffer data corruption due either to variations in the manufacturing process or variations in operating conditions (temperature gradients, electromagnetic noise, aging, etc.).
For this reason, bit error ratio (BER) measurements are performed during design, development, and testing to ensure an interconnect is fully operational and to eventually tune transmitter/receiver setting in order to guarantee a good error performance. However, online BER measurements (during normal operation of a product) typically are not currently available, particularly in high-speed interconnects as such online techniques require high power consumption, computational complexity, or a loopback path between transmitter and receiver, all of which prevent efficient operation of an interconnect.